1) Field of the Invention
The present invention relates to semiconductor memory devices such as a static random access memory (SRAM) having a repeater circuit.
2) Description of the Related Art
Recently, there has been a considerable increase in the capacity of SRAM macros included in semiconductor chips. As a result, longer decoder lines, bit lines, write signal lines, and read signal lines are required. However, the longer signal lines cause a delay in signal propagation speed and an increase in power consumption. One approach to avoid the decrease in the signal propagation speed is to divide a cell array in the SRAM macro into a plurality of blocks, divide the various signal lines mentioned above, and insert a repeater circuit between the lines.
For example, conventional semiconductor memory devices are known that have a cell array divided into a plurality of blocks (for example, refer to Japanese Patent Laid-Open Publication No. 2004-79077). Such a semiconductor memory device includes a plurality of memory blocks, a plurality of data buses, a plurality of buffer circuits, a block activating circuit, and buffer controlling circuits. The data buses are provided for each of the memory blocks. The buffer circuits are provided for each of the memory blocks and connects the data buses in series by relaying data on the data buses. The block activating circuit outputs a plurality of block selection signals for each of the memory blocks and selectively activates a memory block by asserting a block selection signal. The buffer controlling circuits are provided for each of the memory blocks and activate a buffer circuit when the corresponding block selection signal is asserted or when a buffer circuit in a memory block adjacently located in an upstream direction on a data bus is activated.
Semiconductor memory devices having a different configuration are also known (for example, refer to Japanese Patent Laid-Open Publication No. S58-199490). In such a semiconductor memory device, an internal data bus is divided into a plurality of buses, and these buses are coupled by a multi-directional information transferring unit capable of separating the divided buses based on their capacities and allowing mutual signal transfer among these buses.
Other semiconductor memory devices having a different configuration are also known (for example, refer to Japanese Patent Laid-Open Publication No. H10-269765). Such a semiconductor memory device includes a plurality of memory mats, a master control circuit, a plurality of local control circuits, and a buffer unit. Each of the memory mats has a plurality of memory cells disposed in a matrix format. The master control circuit generates, for the memory mats in common, an internal address signal and an internal control signal according to an external signal including an address signal. The local control circuits are respectively provided for the memory mats, and controls an access operation to a memory cell of a corresponding memory mat according to the internal address signal and the internal control signal from the master control circuit. The buffer unit is provided between the master control circuit and each of the local control circuit, and performs a buffer process on a signal from the master control circuit for transfer to each of the local control circuit.
A conventional semiconductor memory device having a cell array divided into a plurality of blocks and having a repeater circuit as described above is described below. FIG. 1 is a block diagram of the relevant parts of such a conventional semiconductor memory device having a cell array divided into two blocks, that is, a first block 1 and a second block 2. [N+2] signal lines are provided, including n control signal lines (3a and 3b; and 4a and 4b) (in FIG. 1, only two control lines are shown), a first block selection signal line (5a and 5b) for selecting the first block 1, and a second block selection signal line (6a and 6b) for selecting the second block 2.
The n control signal lines (3a and 3b; and 4a and 4b) transmit a word selection signal, a column selection signal, a read control signal, a write control signal, etc., respectively. The first block selection signal line (5a and 5b) transmits a signal for selecting the first block 1 (hereinafter, “a first block selection signal”), and the second block selection signal line (6a and 6b) transmits a signal for selecting the second block 2 (hereinafter, “a second block selection signal”).
The n control signal lines (3a and 3b; and 4a and 4b), the first block selection signal line (5a and 5b), and the second block selection signal line (6a and 6b) are respectively divided, by a pair of inverters 7 and 8 connected in series, into two portions. One is first portions 3a, 4a, 5a, and 6a which are connected to the first block 1, and the other is second portions 3b, 4b, 5b, and 6b which are connected to the second block 2. The [n+2] pairs of inverters 7 and 8 form a repeater circuit 9.
In the structure shown in FIG. 1, the first block 1 is selected when the first block selection signal on the first portion 5a of the first block selection signal line (5a and 5b) is asserted. Normally at this time, the second block selection signal on the second block selection line (6a and 6b) is negated (in other words, the second block 2 is not selected). In this state, when any one of control signals on the first portions 3a and 4a of the control signal lines (3a and 3b; and 4a and 4b) becomes negated or asserted, a potential change is output to the second portions 3b and 4b via the inverters 7 and 8, thereby changing a control signal on the second portion 3b or 4b. However, the second block 2 is not operated since the second block selection signal is negated.
Table 1 is a list of block selection signals S1 and S2, control signals C1 and C2, and corresponding operation modes of the semiconductor memory device. S1 denotes a block selection signal on the first block selection signal line (5a and 5b). S2 denotes a block selection signal on the second block selection signal line (6a and 6b). C1 denotes a control signal on the first portions 3a and 4a, and C2 denotes a control signal on the second portions 3b and 4b, of the control signal lines (3a and 3b; and 4a and 4b). Let us assume that each block selection signal and each control signal is active when it is at a logical “H” (High level). In Table 1, “X” represents undefined. The same goes for other tables.
TABLE 1S1S2C1C2Operation modeLLXXstand-byHLLLthe first block is selected but not operatedLHLLthe second block is selected but not operatedHLHHthe first block is operatedLHHHthe second block is operated
In the conventional semiconductor memory device having the repeater circuit 9 described above, the control signals on the control signal lines (3a and 3b; and 4a and 4b) are transferred to the second block 2 even when the second block 2 is not selected. Therefore, each of the control signal lines (3a and 3b; and 4a and 4b) is driven throughout its length even though each line is divided into the first portions 3a and 4a and the second portions 3b and 4b, respectively.
Thus, the capacity of each of the control signal lines (3a and 3b; and 4a and 4b) is the same as that in the case where no repeater circuit 9 is provided. As a result, in the conventional semiconductor memory device, power consumption is barely reduced even though each of the control signal lines (3a and 3b; and 4a and 4b) is divided by the repeater circuit 9.